1. Field of the Invention
The present invention relates to a capacitor element using a semiconductor, for example, a MOS capacitor. Also, the present invention relates to a memory element using such a MOS capacitor, for example, a MOS memory. Furthermore, the invention relates to a semiconductor device including such a capacitor element and a memory element.
2. Description of the Related Art
In recent years, semiconductor devices have been outstandingly developed. In accordance with the development of highly-integrated, high-density semiconductor devices, the miniaturization of each element pattern that is formed therein has been rapidly carried out. High speed, small, high-capacity semiconductor devices have been required insistently. In order to realize the high speed, small, high-capacity semiconductor devices, each element pattern included therein has been necessary to be miniaturized increasingly.
In particular, a memory element is a representative example of such elements. It is necessary to reduce not only the sizes of respective elements such as a transistor and a capacitor but also the size of a memory including these elements to reduce an occupation area thereof. In order to realize the reduction in occupation area, various kinds of structures have been developed actively (e.g., the patent document 1 and the patent document 2).    [Patent Document 1]: Japanese Patent No. 2979098    [Patent Document 2]: Japanese Patent No. 3182758
In order to form MOS capacitors having different capacitance as storage capacitor elements of a memory and a panel by using the conventional technique, the electrode area is necessary to be changed for each MOS capacitor. Therefore, there has been a problem in which the number of manufacturing process is increased.
Also, in order to hold negative and positive potentials, an n-type MOS capacitor and a p-type MOS capacitor have been necessary to be formed separately as the storage capacitor elements such as the memory and the panel.
Accordingly, with respect to a memory, a panel or the like that requires MOS capacitors having different amounts of capacitance over one substrate, or a memory, a panel or the like that requires both an n-type MOS capacitor and a p-type MOS capacitor, the number of manufacturing process is increased, and therefore, the throughput is reduced.